In general, the present invention relates to a microcomputer and a semiconductor integrated circuit including an embedded data-transfer device. More particularly, the present invention relates to an effective technology applicable to typically a single-chip data processor or a single-chip microcomputer.
A typical microcomputer comprises functional blocks such as a CPU (central processing circuit) serving as a nucleus component, a ROM (read-only memory) for storing a program, a RAM (random-access memory) for storing data and an input/output circuit for inputting and outputting data which are built on a semiconductor substrate as described on pages 540 to 541 of a publication entitled xe2x80x9cLSI Handbookxe2x80x9d published by Ohm Corporation on Nov. 30, 1984.
The microcomputer may include an embedded DMAC (direct memory access controller) which is capable of transferring data independently of the CPU. An example of a document describing such a microcomputer is Japanese Patent Laid-open No. Hei 5-307516.
In addition, a microcomputer may have an external-bus-right releasing function for releasing a right to make an access to an external bus to an external device. After the right to make an access to the external bus has been granted to an external device, however, the CPU is still capable of carrying out an operation using an internal bus such as an operation to read out information from the ROM. If a DMAC is connected to the external bus of the microcomputer as an external device, it is possible to transfer data through the external bus using the external DMAC in parallel to an operation based on the internal bus such as an operation to read out information from the ROM. Japanese Patent Laid-open No. Hei 4-24854 is an example of a document describing a microcomputer wherein a CPU""s operation based on an internal bus and a DMAC""s operation based on an external bus can be carried out concurrently. Japanese Patent Laid-open No. Hei 1-187682 is an example of a document describing the use of 2 DMACs operating concurrently.
The inventor of the present invention studied a microcomputer including an embedded DMAC, a system employing such a microcomputer and a system comprising a microcomputer with a function to grant a right to make an access to an external bus and an external DMAC connected to the external bus.
In the first place, in the case of a microcomputer including an embedded DMAC, the DMAC can be activated by an interrupt request and is capable of operating in modes such as a repeat mode and a block-transfer mode. In a system such as a printer, a microcomputer including an embedded DMAC is suitable for a plurality of processes to control a stepping motor, control of data to be printed on the printer and operations to store incoming data into a memory, allowing a plurality of data-transfer channels to be provided.
Even though the data-transfer control of the DMAC is executed independently of the operation of the CPU, however, data is transferred by the DMAC through a bus shared by the CPU so that bus cycles required for transferring the data inevitably halt the operation of the CPU. Assume for example that data is transferred by an embedded DMAC from a RAM to an input/output circuit. In this case, a data transfer requires 6 states, i. e., 2 states for an access to the RAM, 3 states for an access to the input/output circuit and 1 state for a dead cycle. During these 6 states, the CPU is not capable of using the bus. 1 state is typically but not limited to 1 period of a reference clock signal of a data processing LSI such as a microcomputer.
In a system comprising a microcomputer with a function to grant a right to make an access to an external bus and an external DMAC connected to the external bus, on the other hand, an operation using an internal bus such as an operation carried out by a CPU to read out data from a ROM can be carried out concurrently with an operation carried out by the external DMAC to transfer data through the external bus.
In an operation to grant a right to make an access to the external bus from the microcomputer to an external component such as DMAC, however, the microcomputer must exchange signals such as a request signal and an acknowledge signal with the external component. To be more specific, the microcomputer must recognize a request signal generated by the external component and issue an acknowledge signal to the external component to recognize the request signal, spending an extra time for the exchange of the signals. In addition, in order to avoid a bus-usage collision between the microcomputer and the external DMAC, it is necessary to set a time during which both the microcomputer and the external DMAC are not using the shared bus. Such a time most likely becomes an overhead which has nothing to do with the actual operation to transfer data through the shared bus. When an overhead is required before and after each transfer of data, the overheads have a magnitude which is hardly negligible in comparison with the data transfer period itself. Moreover, if a general-purpose external DMAC is employed, some functions of the DMAC are not utilized. Thus, such a DMAC can not be said to be a cost-effective solution. If a DMAC suitable for a system is developed individually for each system only because a general-purpose DMAC is not cost effective as described above, however, the development of such a DMAC specialized for a system will incur as much a cost as the development of a new LSI separate from the microcomputer, most likely raising a manufacturing-cost problem.
Take a system such as a printer as an example. During a printing operation, it is necessary to drive a stepping motor for driving the printing mechanism and to carry out data processing peculiar to the system such as creation of data to be printed. It is also necessary to receive data from a host apparatus asynchronously with the operating state of the printer. Other systems employing a microcomputer and a DMAC include digital equipment such as a digital video deck, a DVD (digital video disc) drive and a digital TV. In such systems, it is necessary to perform signal processing such as a process to decode a digital signal and a process to encode audio and/or analog signals. In the digital equipment, it is also necessary to input and output a digital signal. In addition, it is also conceivably necessary to drive a motor for driving a medium such as a tape or a disc used for recording a digital signal. In order to increase the speed, the performance and the precision of these pieces of equipment such as the printer, the digital video deck, the DVD drive and the digital TV, it is necessary to enhance the processing power of the microcomputer employed thereby.
The needs described above led the inventor of the present invention to come up with an idea of incorporating an embedded data-transfer device such as a DMAC in a microcomputer and to discover the importance of enhancement of the total processing performance of the whole system through the use of the microcomputer.
With regard to the importance of the total processing performance enhancement, the inventor disclosed an invention of a microcomputer in Japanese Patent Laid-open No. Hei 11-36949. According to the disclosed invention, the microcomputer employs: an embedded data-transfer unit such as a direct memory access controller for controlling a transfer of data through an external bus of the microcomputer; and an embedded bus-control means for allowing an instruction using an internal bus to be executed by a data processing unit such as a CPU concurrently with a transfer of data through the external bus carried out by the data-transfer unit. The data-transfer unit is designed mainly for use in data-transfer control external to the microcomputer. In addition, in a dual-address transfer carried out by the data-transfer unit, data read out from an address in an external source is temporarily stored in a latch circuit such as an input/output port composing a bus-interface means for interfacing with an external component. Thus, in a transfer of data from an external source location to an external destination location, the data can be transferred from the external source location directly to the external destination location without the need to take the data to the embedded data-transfer unit. It is therefore unnecessary to provide a data bus for taking data being transferred to the data-transfer unit. The elimination of such a data bus contributes to the shrinkage of the physical size of the microcomputer.
Furthermore, the inventor also studied a case where, in a transfer of data through the external data bus, transfer control information such as a packet command used for specifying details of the data transfer is transferred prior to the transfer of the actual data. In some cases, the transfer control information includes data such as the number of transferred words which is required in the transfer control.
With regard to such transfer control information, the inventor disclosed an invention of a microcomputer in Japanese Patent Laid-open No. Hei 11-239514. The disclosed microcomputer is provided with an embedded buffer for delivering transfer control information to a data processing unit of the microcomputer in addition to the data-transfer unit and the bus-control means described above.
Transfer control information needs to be immediately analyzed by a data processing unit such a CPU and it is necessary to set a data transfer following the transfer control information and conforming to transfer details indicated by a result of the analysis typically in the data-transfer unit. Thus, storing the transfer control information in an external RAM serving as a buffer memory is not a good solution. This is because the CPU reads out information from an external memory in an access with a speed which is not so high as an access to an embedded memory or an I/O register. In addition, the external bus cannot probably be made as wide as the bus width of the CPU. Moreover, if the data-transfer unit is carrying out a transfer of data through another data-transfer channel, it will be quite within the bounds of possibility that the speed to process the transfer control information is reduced due to a contention for the external bus with the transfer of data. Furthermore, from the memory-management point of view, it is not desirable to store data and transfer control information in the same memory. In addition, in an attempt to read out the transfer control information from the external memory, the CPU needs to carry out special processing for verification of the existence of the transfer control information such as an operation to reference an address register employed in the data-transfer unit.
It is thus an object of the present invention addressing the problems described above to provide a microcomputer including an embedded data-transfer unit such as a DMAC for enhancing the data processing total performance and to provide a semiconductor integrated circuit with such a microcomputer embedded therein.
It is another object of the present invention to provide a microcomputer which has a function of supplying transfer control information such as a packet command used for specifying details of a data transfer to a data processing unit for analyzing the information with a high degree of efficiency and allows an increase in circuit scale caused by the function to be reduced to a minimum, and to provide a semiconductor integrated circuit with such a microcomputer embedded therein.
It is still another object of the present invention to provide a microcomputer which allows increases in physical and logical scales each to be reduced to a minimum and is capable of executing control of a data transfer through an external bus of the microcomputer concurrently with a CPU operation such as an access made by a CPU embedded in the microcomputer to an internal bus.
It is a further object of the present invention to provide a microcomputer system which is capable of executing control of a data transfer between a microcomputer employed in the system and a component external to the microcomputer concurrently with internal processing carried out by the microcomputer at a small processing overhead and allows an increase in physical scale to be reduced to a minimum.
It is a still further object of the present invention to provide an apparatus employing a microcomputer which is capable of carrying out a transfer of data between the apparatus and other equipment concurrently with processing internal to the apparatus.
The above and other objects as well as characteristics of the present invention will probably become more apparent from a study of the following description with reference to accompanying diagrams.
Outlines of representatives of the present invention disclosed in this specification are described in brief as follows.
(1) A microcomputer has a data-transfer unit 4 such as a direct access memory controller for controlling a transfer of data through an external bus of the microcomputer. The microcomputer is also provided with a bus-control means 12 for allowing an instruction using an internal bus to be executed by a data processing unit such as a CPU concurrently with a transfer of data through the external bus carried out by the data-transfer unit. As a result, the processing performance of the microcomputer can be enhanced. In other words, data can be transferred through the external bus without deteriorating the processing performance of the CPU. To put it in detail, the bus-control means 12 employed by the microcomputer is used for implementing arbitration of requests for a bus-access right and executing bus control. The bus-control means 12 allows an operation to make an access only within the microcomputer by using first internal buses IDB and IAB connected to a data processing unit to be carried out concurrently with an operation performed by the data processing unit connected to a second internal bus (or an external-address internal bus) EXAB to make an access to an external address space through a bus-interface means.
Since an instruction using an internal bus can be executed by a data processing unit such as a CPU concurrently with a transfer of data through the external bus carried out by the data-transfer unit, the processing performance of the microcomputer can be enhanced. As a result, data can be transferred through the external bus without degrading the processing performance of the microcomputer.
The bus-control means can be configured to comprise an internal-bus controller and an external-bus controller. The external-bus controller can be designed so as to allow the address space to be divided as well as bus specifications such as the type of a memory, the bus width and the number of access states to be set. In addition, the external-bus controller can be configured so as to arbitrate a request for a right to make an access to the external bus made by the data processing unit such as the CPU which serves as a bus master embedded in the microcomputer, a request for a right to make an access to the external bus made by the data-transfer unit and a request for a right to make an access to the external bus made by a component external to the microcomputer. Thus, control of internal accesses using the first internal buses IAB and IDB made by the data processing unit concurrently with accesses to the external bus made by the data-transfer unit in the first place, and control to arbitrate accesses to the external bus made by the data-transfer unit made and accesses to the external bus using the first internal buses IAB and IDB made by the data processing unit in the second place can be implemented by separated pieces of logic with ease. As a result, the control logic or the control system can be made simple with ease while, at the same time, an increase in control logical scale can be suppressed easily.
At that time, by supplying information such as an address output by the data-transfer unit to the bus-interface means through a dedicated signal line such as the second internal bus EXAB, an operation to control state transitions of the data-transfer unit can be made simple, and a simple operation contributes to reduction of the logical scale thereof.
In addition, since the external-bus controller arbitrates a request for a right to make an access to the external bus made by the data processing unit such as the CPU embedded in the microcomputer, a request for a right to make an access to the external bus made by the data-transfer unit embedded in the microcomputer and a request for a right to make an access to the external bus made by a component external to the microcomputer, it is possible to reduce an overhead which is incurred when a right to make an access to the external bus is transferred from the data processing unit to the data-transfer unit or vice versa and to enhance the processing performance.
A storage means 5 such as a ROM for storing programs to be executed by the data processing unit such as the CPU can be made selectable by specification of an operating mode so as not to include or exclude a vector of the data processing unit such as the CPU. It is thus possible to store general processing programs in an external ROM and a program requiring execution at a high speed or the like in an embedded ROM. As a result, the degree of freedom to use the microcomputer such as flexibility against program changes can be increased.
Main factors to activate the data-transfer unit and transfer modes can be limited only to functions required in a transfer of data through the external bus. Thus, the physical size can be reduced.
In addition, in a dual-address transfer carried out by the data-transfer unit, data read out from an address in an external source is temporarily stored in a latch circuit 72L such as an input/output port composing a bus-interface means 12 for interfacing with an external component. Thus, in a transfer of data from an external source location to an external destination location, the data can be transferred from the external source location directly to the external destination location without the need to take the data to the embedded data-transfer unit. It is therefore unnecessary to provide a data bus for taking data being transferred to the data-transfer unit.
If the data-transfer unit also supports a single-address transfer, the number of bus cycles required for a transfer of data can be reduced, allowing the processing performance of the microcomputer to be enhanced further.
The data-transfer unit is allowed to have a plurality of data-transfer channels. In such a configuration, a signal requesting activation of an external data transfer can be allocated to each of the data-transfer channels. As a result, it is possible to increase the degree of freedom to execute control of a data transfer in the microcomputer and the processing performance of the microcomputer.
In addition to the data processing unit such as the CPU and the data-transfer unit, a second data-transfer unit 3 such as a general-purpose DMAC capable of supporting control of data transfers inside and outside the microcomputer can also be embedded in the microcomputer. The second data-transfer unit is connected to the internal bus which is provided originally for the conventional microcomputer. In comparison with a configuration securing the number of necessary data-transfer channels in a general-purpose DMAC for controlling transfers of data inside and outside the microcomputer, a data-transfer unit specialized for transfers of data through the external bus has a configuration customized to control of data transfers through the external bus. Thus, an increase in logical scale can be reduced to a minimum even if the second data-transfer unit has a number of required data-transfer channels as a whole.
If the bus-control means allows control to refresh a DRAM or the like to be executed, requests for a right to make an access to the external bus are arbitrated by treating a refresh timer for refreshing the DRAM like a source requesting a right to make an access to the external bus.
The second data-transfer unit connected to the first internal bus and the data-transfer unit tailored to control of data transfers through the external bus can be built in a single module so that they can be used with a limited number of data-transfer channels conceded to each other.
(2) A bus-interface means 72 utilized in an access to the external bus made by the data-transfer unit in the microcomputer is provided with a plurality of buffer-register means EXDiDRm. The data-transfer unit has memory specification means 40, 41 and 72C such as address registers for specifying a memory means such as a memory device, a buffer specification means 48 for specifying one of the buffer-register means independently of the memory specification means and a mode specification means for specifying an operating mode of a data transfer. A transfer control means executes control of a data transfer on the basis of the states of the mode specification means, the memory specification means and the buffer specification means.
The mode specification means is provided with a first information field for determining whether to specify either a source location or a destination location of a data transfer by using the buffer specification means or to specify both the source and destination locations by using the memory specification means.
In a transfer of data through the external bus, any one of the buffer-register means can be used as a location indicated by either a source or destination address. One of the buffer-register means is specified by using the buffer specification means which is typically implemented by a transfer-count register instead of using the memory specification means which is a means for specifying another memory device by using typically an address or an acknowledge signal. The buffer-register means is used for inputting and outputting data from and to the external bus during a transfer of the data carried out by the data-transfer unit. The data processing unit 2 such as the CPU is capable of reading out and writing data from and into the buffer-register means through the internal bus.
As described above, transfer control information such as a packet command may be transferred through the external bus prior to a transfer of actual data. In this case, one of the buffer-register means can be used for receiving the transfer control information. As described above, one of the buffer-register means can be specified without using an address or an acknowledge signal. Since a bus cycle is not required in selecting one of the buffer-register means, a transfer of data such as reception of transfer control information can be carried out at a high speed. The data processing unit such as the CPU is capable of reading out data from a buffer-register means through the internal bus without using the external bus, making it possible to read out transfer control information from the buffer-register means at a higher speed. Since the buffer specification means allows information to be stored in a predetermined buffer-register means, the data processing unit such as the CPU does not have to carry out processing such as recognition of an address of information like a packet command. Thus, processing such as an analysis of transfer control information can be carried out by the data processing unit at a high speed and, in accordance with a result of the analysis, the data processing unit is capable of performing processing such as re-setting a data-transfer control condition for the data-transfer unit, recognition of the number of data-transfer words and changing of the location of a data-transfer destination from a buffer register to an address in a memory with a higher degree of efficiency. As a result, the data processing unit is capable of increasing the efficiency of switching to a data-transfer operation that reflects the new transfer control information.
A transfer-count register 48 can also be used as the buffer specification means. In this case, when the first information field selects the use of the buffer specification means for specification of one of the source and destination locations described above, for example, the whole or a portion of the transfer-count register can also be used in the selection of a buffer-register means. If the first information field selects the use of the memory specification means for specification of both the source and destination locations described above, on the other hand, the transfer-count register executes its native function of counting the number of transfer-data words.
The native function of the transfer-count register to count the number of transfer-data words is implemented through an arithmetic-processing means for receiving contents of the transfer-count register and returning a result of arithmetic processing to the transfer-count register. The arithmetic-processing means is also used in arithmetic processing to increment the contents of an address register which serves as the memory specification means.
The mode specification means may further include a second information field MD1. With the first information field selecting the use of the buffer specification means for specification of one of the source and destination locations described above in a transfer of data (MD2=1), the second information field MD1 determines whether to use selection of the other location as a selection of a location in a dual-addressing mode or a single-addressing mode. The other location serves as a partner of a buffer-register means specified by the buffer specification means in a transfer of data. The mode specification means may further include a third information field ND0 for determining whether to use the buffer-register means specified by the buffer specification means as a source location or a destination location.
The mode specification means may further include a fourth information field RPE and a fifth information field RPB0 to RPB2 for allowing sequential selection of source and destination locations to be carried out repeatedly.
With the first information field selecting the use of the buffer specification means for specification of one of the source and destination locations described above, the fourth information field serves as an area for storing information requesting the transfer control means 45 to: use a portion TCRL of the transfer-count register as the buffer specification means; and transfer contents of the remaining portion TCRH of the transfer-count register to the portion TCRL when a result of arithmetic processing returned from the arithmetic-processing means to the portion TCRL reaches a predetermined value.
By specifying this operation in the fourth information field, it is possible to control consecutive transfers of data while specifying a plurality of buffer-register means repeatedly in a predetermined order and to make the control simple. That is, the number of times a transfer condition is set by the data processing means for the data-transfer unit can be reduced considerably and a small number of such times facilitates reduction of a load borne by the data processing unit.
With the first information field selecting the use of the buffer specification means for specification of one of the source and destination locations described above, the fifth information field serves as an area for storing information requesting the transfer control means 45 to drive the arithmetic-processing means to: carry out arithmetic processing with a condition of a fixed logic value of higher-order bits of information input from the address register than a predetermined bit of the information; and return a result of the arithmetic processing to the address register.
By specifying this operation in information in the fifth field, the value of an address specification means such as the address register can be updated repeatedly in a sequential manner, allowing a buffer memory such as an external RAM to be used as a ring buffer. When address information in the address specification means is incremented or decremented by the arithmetic-processing means in the repetitive address updating operations carried out in order to use an external buffer memory as a ring buffer, the logic value of high-order bits of the address information than a predetermined bit of the address information is not changed. In other words, propagation of a carry or a borrow crossing the predetermined bit is avoided. As a result, the function of a ring buffer can be implemented with a minimum physical scale. Even though start and end addresses of the ring buffer can not be specified in a completely arbitrary manner, there is conceivably no big problem which will be encountered when a memory with a large storage capacity such as an external RAM is utilized as a ring buffer. Since repetitive operations can be carried out with the scheme described above, it is possible to reduce a load such as interrupt processing requested to the data processing unit such as the CPU.
(3) In a data processing system or a microcomputer system employing the microcomputer including the data-transfer unit and the bus-control means, the bus-interface means of the microcomputer is connected to the external bus which is connected to a RAM.
A data-communication circuit connected to the external bus can also be provided. The data-communication circuit supplies a signal requesting activation of an external data transfer to the data-transfer unit of the microcomputer. If a right to make an access to the external bus is granted by the bus-control means to the data-transfer unit, the data-transfer unit requests the data-communication circuit to transfer data by outputting a signal allowing a transfer of data through the external bus or a predetermined address in conjunction with a read or write signal to the data-communication circuit.
If the first information field selects the use of the memory specification means for specification of both the source and destination locations, the data-transfer unit is capable of controlling a transfer of data between the data-communication circuit and the RAM in the microcomputer system in a single-addressing mode. At that time, a signal allowing a transfer of data through the external bus is generated to request the data-communication circuit to transfer data whereas an access to the RAM is made by using an access address signal.
If the first information field selects the use of the buffer specification means for specification of one of the source and destination locations, the data-transfer unit is capable of controlling a transfer of data between the data-communication e circuit and the buffer-register means in the microcomputer system in a manner corresponding to the single-addressing mode. At that time, the data-transfer unit requests the data-communication circuit to serve as a source generating transfer control information typically in the form of a packet command by using a signal allowing a transfer of data through the external bus, and uses the buffer specification means for specifying a buffer-register means.
The data processing unit fetches the transfer control information such as a packet command transferred to the specified buffer-register means for an analysis and changes the transfer condition of the data-transfer unit in accordance with a result of the analysis.
With the first information field selecting the use of the memory specification means for specification of both the source and destination locations, the data-transfer unit with the transfer condition modified is capable of controlling a transfer of data between the data-communication circuit and the RAM in the microcomputer system in a single-addressing mode, and requests the data-communication circuit to transfer data information following the packet command by using a signal allowing a transfer of data through the external bus, supplying an access address specified by the memory specification means to the RAM.
Thus, when transfer control information such as a packet command is transferred prior to a transfer of actual data, the transfer control signal can be received by a buffer-register means in the microcomputer instead of being stored in the external RAM (or a buffer memory). As a result, the data processing unit such as the CPU is capable of immediately switching its operation to an analysis of transfer control information without the need to initiate an external-bus cycle and capable of setting a transfer of data according to data-transfer details obtained as a result of the analysis of the transfer control information in the data-transfer unit quickly and transiting to a transfer of data information. Since the external RAM is used for storing only net data, the processing of data can be made simple as well.
Typical transfer protocols based on the data transfer information are the IEEE1394 and the USB (Universal Serial Bus).
The whole microcomputer system or the system excluding the external RAM can be integrated into a single semiconductor chip.